1 03/12/02 supertex inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." supertex does not assume responsibility for use of devices described and limits its liabi lity to the replacement of devices determined to be defective due to workmanship. no responsibility is assumed for possible omissions or inaccuracies. circuitry and specifications are subject to c hange without notice. for the latest product specifications, refer to the supertex website: http://www.supertex.com. for complete liability information on all supertex products, refer to the most curre nt databook or to the legal/disclaimer page on the supertex website. absolute maximum ratings supply voltage, v dd 1 -0.5v to +7.5v output voltage, v nn 1 v dd + 0.5v to -95v logic input levels 1 -0.3v to v dd +0.3v ground current 2 1.5a continuous total power dissipation 3 plastic 1200mw ceramic 1900mw operating temperature range plastic -40 c to +85 c ceramic -55 c to +125 c storage temperature range -65 c to +150 c lead temperature 1.6mm (1/16 inch) from case for 10 seconds 260 c notes: 1. all voltages are referenced to v ss . 2. limited by the total power dissipated in the package. 3. for operation above 25 c ambient derate linearly to maximum operating temperature at 20mw/ c for plastic and at 19mw/ c for ceramic. hv57009 64-channel serial to parallel converter w ith p-channel open drain controllable output current general description the hv570 is a low-voltage serial to high-voltage parallel con- verter with p-channel open drain outputs. this device has been designed for use as a driver for plasma panels. the device has two parallel 32-bit shift registers, permitting data rate twice the speed of one (they are clocked together). there are also 64 latches and control logic to perform the blanking of the outputs. hv out 1 is connected to the first stage of the first shift register through the blanking logic. data is shifted through the shift registers on the logic low to high transition of the clock. the dir pin causes ccw shifting when connected to v ss , and cw shifting when connected to v dd . a data output buffer is provided for cascading devices. this output reflects the current status of the last bit of the shift register (hv out 64). operation of the shift register is not affected by the le (latch enable), or the bl (blanking) inputs. transfer of data from the shift registers to latches occurs when the le input is high. the data in the latches is stored when le is low. the hv570 has 64 channels of output constant current sourcing capability. they are adjustable from 0.1 to 2.0ma through one external resistor or a current source. features ? processed with hvcmos technology ? 5v cmos logic ? output voltage up to -85v ? output current source control ? 16mhz equivalent data rate ? latched data outputs ? forward and reverse shifting options (dir pin) ? diode to v dd allows efficient power recovery ? hi-rel processing available package options device 80-lead quad ceramic gullwing 80 lead quad plastic gullwing die 80 lead quad ceramic gullwing (mil-std-833 processed*) hv57009 hv57009dg hv57009pg HV57009X rbhv57009dg * for hi-rel process flows, refer to page 5-3 of the databook. ordering information
2 symbol parameter min max units conditions i dd v dd supply current 15 ma v dd = v dd , max f clk = 8mhz i nn high voltage supply current -10 a outputs off, hv out = -85v (total of all outputs) i ddq quiescent v dd supply current 100 a all inputs = v dd , except +in = v ss = gnd v oh high-level output data out v dd -0.5 v i o = -100 a hv out +1 v dd vi o = -2ma v ol low-level output data out +0.5 v i o = 100 a i ih high-level logic input current 1 av ih = v dd i il low-level logic input current -1 av il = 0v i cs hv output source current -2 ma v ref = 2v, r ext = 1k, see figures 8a and 8b -0.1 ma v ref = 0.1v, r ext = 1k, see figure 8a and 8b ? i cs hv output source current for i ref = 2.0ma 10 % v ref = 2v, r ext = 1k electrical characteristics dc characteristics (all voltages are referenced to v ss , v ss = 0, ta = 25 c) symbol parameter min max units conditions f clk clock frequency dc 8 mhz per register t wl , t wh clock width high or low 62 ns t su data set-up time before clock rises 10 ns t h data hold time after clock rises 15 ns t on , t off time for latch enable to hv out 500 ns c l = 15pf t dhl delay time clock to data high to low 70 ns c l = 15pf t dlh delay time clock to data low to high 70 ns c l = 15pf t dle delay time clock to le low to high 25 ns t wle width of le pulse 25 ns t sle le set-up time before clock rises 0 ns t r , t f maximum allowable clock rise and fall time 100 ns (10% and 90% points) ac characteristics (logic signal inputs and data inputs have t r , t f 5ns [10% and 90% points] for measurements) notes 1: current going out of the chip is considered negative. hv57009
3 hv57009 v dd input logic inputs data out logic data output v dd v dd input to internal circuits v ss v ss v ss analog input v dd i cs hv out p ctl high voltage output symbol parameter min max units v dd logic supply voltage 4.5 5.5 v hv out hv output off voltage -85 v dd v v ih high-level input voltage v dd - 1.2v v dd v v il low-level input voltage 0 1.2 v f clk clock frequency per register dc 8 mhz t a operating free-air temperature plastic -40 +85 c ceramic -55 +125 c note: power-up sequence should be the following: 1. connect ground. 2. apply v dd . 3. set all inputs to a known state. power-down sequence should be the reverse of the above. recommended operating conditions figure 1: input and output equivalent circuits
4 hv57009 le hv out w/ data input low previous i o = i ref previous i o = 0 i o = 0 i o = i ref data valid 50% 50% data input clk data out 50% 50% 50% t su t h t wl t wh 50% t dlh t dhl 50% t wle t dle t sle 50% 50% t on 10% hv out w/ data input high 90% 90% 10% t off v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss v dd hv out (off) v dd hv out (off) 10% 90% 90% 10% 50% t f t r figure 2: switching waveforms
5 hv57009 hv out 1 hv out 2 hv out 3 hv out 33 hv out 34 hv out 35 latch latch latch latch programmable current v dd v ss bl le sr2 sr1 clk dir v bp +in -in hv out 32 hv out 64 d i/o 2a d i/o 1a d i/o 2b d i/o 1b i/o i/o inputs outputs function data in clk le bl dir shift reg hv outputs data out all o/p high x x l h h h h data stored in latches x l h i/o relation h h l h l h h h x l h x d i/o 1-2a d i/o 1-2a d i/o 1-2b d i/o 1-2b figure 4: function table x x x x h h l l * l....l h....h * q n q n+1 q n q n+1 q n q n-1 q n q n-1 on on off new on or off previous on or off previous on or off new on or off notes: * = dependent on previous stage? state. see figure 7 for d in and d out pin designation for cw and ccw shift. h = v dd (logic)/v nn (hv outputs) l = v ss note: each sr (shift register) provides 32 outputs. sr1 supplies outputs 1 to 32 and sr2 supplies outputs 33 to 64. figure 3: functional block diagram inversion of stored data data falls through (latches tansparent) * l h * d i/o 1-2b d i/o 1-2b d i/o 1-2a d i/o 1-2a
6 hv57009 65 80 1 24 25 40 41 64 index top view 80-pin gullwing package 25 26 36 37 hv 32 hv 2 hv 1 hv 33 hv 63 hv 64 pin sr1 sr2 out out out out out out dir = v dd ; cw (hv out 1 hv out 64) dir = v ss ; ccw (hv out 64 hv out 1) cw cw pin function 1hv out 24 2hv out 23 3hv out 22 4hv out 21 5hv out 20 6hv out 19 7hv out 18 8hv out 17 9hv out 16 10 hv out 15 11 hv out 14 12 hv out 13 13 hv out 12 14 hv out 11 15 hv out 10 16 hv out 9 17 hv out 8 18 hv out 7 19 hv out 6 20 hv out 5 21 hv out 4 22 hv out 3 23 hv out 2 24 hv out 1 25 d i/o 1a 26 d i/o 2a 27 n/c 28 n/c 29 le 30 clk 31 bl 32 v ss 33 dir 34 v dd 35 -in 36 d i/o 2b 37 d i/o 1b 38 n/c 39 +in 40 v bp figure 5: pin configurations 80-pin gullwing package pin function 41 hv out 64 42 hv out 63 43 hv out 62 44 hv out 61 45 hv out 60 46 hv out 59 47 hv out 58 48 hv out 57 49 hv out 56 50 hv out 55 51 hv out 54 52 hv out 53 53 hv out 52 54 hv out 51 55 hv out 50 56 hv out 49 57 hv out 48 58 hv out 47 59 hv out 46 60 hv out 45 61 hv out 44 62 hv out 43 63 hv out 42 64 hv out 41 65 hv out 40 66 hv out 39 67 hv out 38 68 hv out 37 69 hv out 36 70 hv out 35 71 hv out 34 72 hv out 33 73 hv out 32 74 hv out 31 75 hv out 30 76 hv out 29 77 hv out 28 78 hv out 27 79 hv out 26 80 hv out 25 figure 6: package outline figure 7: shift register operation notes: 1. pin designation for dir = v dd . 2. a 0.1 f capacitor is needed between v dd and v bp (pin 40) for better output current stability and to prevent transient cross-coupling between outputs. see fig. 8a and 8b. dir = v dd :d i/o 1a d i/o 2a d i/o 2b d i/o 1b dir = v ss :d i/o 2a d i/o 1a d i/o 1b d i/o 2b
7 hv57009 i out hv out v dd v ref i ref r ext +in -in r d * 10k c d * 390pf hv570 logic to other outputs - + 0.1 f v bp v ss v ref i out hv out v dd 0.1 f v bp i ref r ext +in -in r d * 10k c d * 390pf hv570 logic to other outputs -+ v ss since i out = i ref = therefore, if i out = 2ma and v ref = -5v r ext = 2.5k ? . if i out = 1ma and r ext = 1k ? v ref = -1v. if r ext >10k ? , add series network r d and c d to ground for stability as shown. this control method behaves linearly as long as the operational amplifier is not saturated. however, it requires a negative power source and needs to provide a current i ref = i out for each hv570 chip being controlled. if hv out +1v, the hv out cascode may no longer operate as a perfect current source, and the output current will diminish. this effect depends on the magnitude of the output current. given i out and v ref , the r ext can be calculated by using: r ext = v ref = v ref i ref i out the intersection of a set of i out and v ref values can be located in the graph shown below. the value picked for r ext must always be in the shaded area for linear operation. this control method has the advantage that v ref is positive, and draws only leakage current. if r ext > 10k, add series network r d and c d to ground for stability as shown. note: lower reference current i ref , results in higher distortion, ? i cs , on the output. *required if r ext > 10k or r ext is replaced by a constant current source. t ypical current programming circuits figure 8b: positive control figure 8a: negative control ? v ref ? r ext 12345 3 4 5 6 7 8 2 1 0 i out (ma) v ref (v) 100 250 500 r ext = 1k 5k 2k 1235 bordeaux drive, sunnyvale, ca 94089 tel: (408) 744-0100 ?fax: (408) 222-4895 www.supertex.com 03/12/02 ?001 supertex inc. all rights reserved. unauthorized use or reproduction prohibited.
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